Preface, 1.1-1.3
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0:11Introduce the RISC-V Reader1
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0:11Introduce the RISC-V Reader1
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0:11Introduce the RISC-V Reader1
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1:16The back cover2
1:16The back cover2
1:16The back cover2
4:15Pre-preface3
4:15Pre-preface3
4:15Pre-preface3
7:29dannyfritz ped a gah gee
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7:29dannyfritz ped a gah gee
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7:29dannyfritz ped a gah gee
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7:47Pre-preface continued4
7:47Pre-preface continued4
7:47Pre-preface continued4
8:00dannyfritz ped a gah jee
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8:00dannyfritz ped a gah jee
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8:00dannyfritz ped a gah jee
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8:09Pre-preface continued5
8:09Pre-preface continued5
8:09Pre-preface continued5
10:42Background from the publisher6
10:42Background from the publisher6
10:42Background from the publisher6
13:12Check out the GitHub repository7
13:12Check out the GitHub repository7
13:12Check out the GitHub repository7
15:06Dedication8
15:06Dedication8
15:06Dedication8
18:38Preface9
18:38Preface9
18:38Preface9
25:23Plug links.riscy.tv10
25:23Plug links.riscy.tv10
25:23Plug links.riscy.tv10
25:34Preface continued11
25:34Preface continued11
25:34Preface continued11
26:47History of this book12
26:47History of this book12
26:47History of this book12
30:44Chapter 1 - Why RISC-V?13
30:44Chapter 1 - Why RISC-V?13
30:44Chapter 1 - Why RISC-V?13
32:16Chapter 1.1 - Introduction14
32:16Chapter 1.1 - Introduction14
32:16Chapter 1.1 - Introduction14
33:29A few words on deep learning
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33:29A few words on deep learning
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33:29A few words on deep learning
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35:56Chapter 1.1 continued15
35:56Chapter 1.1 continued15
35:56Chapter 1.1 continued15
37:38Figure 1.1 - Members of the RISC-V foundation16
37:38Figure 1.1 - Members of the RISC-V foundation16
37:38Figure 1.1 - Members of the RISC-V foundation16
41:35Figure 1.2 - Growth of the x86 instruction set over its lifetime17
41:35Figure 1.2 - Growth of the x86 instruction set over its lifetime17
41:35Figure 1.2 - Growth of the x86 instruction set over its lifetime17
45:06Figure 1.3 - A description of the x86-32 ASCII adjust after addition instruction18
45:06Figure 1.3 - A description of the x86-32 ASCII adjust after addition instruction18
45:06Figure 1.3 - A description of the x86-32 ASCII adjust after addition instruction18
47:23Chapter 1.2 - Modular vs Incremental ISAs19
47:23Chapter 1.2 - Modular vs Incremental ISAs19
47:23Chapter 1.2 - Modular vs Incremental ISAs19
51:09Reflect on the analogy of a meal becoming a banquet to an ISA growing incrementally
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51:09Reflect on the analogy of a meal becoming a banquet to an ISA growing incrementally
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51:09Reflect on the analogy of a meal becoming a banquet to an ISA growing incrementally
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51:55Chapter 1.2 continued20
51:55Chapter 1.2 continued20
51:55Chapter 1.2 continued20
56:27dannyfritz SSE SSE2 SSE3
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56:27dannyfritz SSE SSE2 SSE3
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56:27dannyfritz SSE SSE2 SSE3
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57:18dannyfritz Not sure, I feel like SSE3 requires SSE2 and SSE
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57:18dannyfritz Not sure, I feel like SSE3 requires SSE2 and SSE
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57:18dannyfritz Not sure, I feel like SSE3 requires SSE2 and SSE
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58:47dannyfritz Oh, like ARB in OpenGL. Interesting
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58:47dannyfritz Oh, like ARB in OpenGL. Interesting
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58:47dannyfritz Oh, like ARB in OpenGL. Interesting
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59:08Chapter 1.3 - ISA Design 10121
59:08Chapter 1.3 - ISA Design 10121
59:08Chapter 1.3 - ISA Design 10121
1:02:37Figure 1.4 - An 8″ diameter wafer of a RISC-V die designed by SiFive22
1:02:37Figure 1.4 - An 8″ diameter wafer of a RISC-V die designed by SiFive22
1:02:37Figure 1.4 - An 8″ diameter wafer of a RISC-V die designed by SiFive22
1:04:12Chapter 1.3 continued23
1:04:12Chapter 1.3 continued23
1:04:12Chapter 1.3 continued23
1:06:14Recall Mike Acton's recommendation from HandmadeCon 201524 to read x86 manuals
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1:06:14Recall Mike Acton's recommendation from HandmadeCon 201524 to read x86 manuals
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1:06:14Recall Mike Acton's recommendation from HandmadeCon 201524 to read x86 manuals
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1:09:39dannyfritz Does that include docs for extensions?
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1:09:39dannyfritz Does that include docs for extensions?
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1:09:39dannyfritz Does that include docs for extensions?
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1:10:00Show the HiFive1 documentation25
1:10:00Show the HiFive1 documentation25
1:10:00Show the HiFive1 documentation25
1:16:02Compare the quantities of documentation for RISC-V and x86
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1:16:02Compare the quantities of documentation for RISC-V and x86
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1:16:02Compare the quantities of documentation for RISC-V and x86
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1:17:35Chapter 1.3 continued26
1:17:35Chapter 1.3 continued26
1:17:35Chapter 1.3 continued26
1:20:55dannyfritz Do RISC-V instructions always operate in 1 cycle?27
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1:20:55dannyfritz Do RISC-V instructions always operate in 1 cycle?27
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1:20:55dannyfritz Do RISC-V instructions always operate in 1 cycle?27
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1:22:52Chapter 1.3 continued28
1:22:52Chapter 1.3 continued28
1:22:52Chapter 1.3 continued28
1:23:38Find the running time equation on the blackboard
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1:23:38Find the running time equation on the blackboard
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1:23:38Find the running time equation on the blackboard
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1:24:53Chapter 1.3 continued, on cycles per instruction29
1:24:53Chapter 1.3 continued, on cycles per instruction29
1:24:53Chapter 1.3 continued, on cycles per instruction29
1:27:23Reflect on this comparison of instruction count between ARM and the smaller RISC-V
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1:27:23Reflect on this comparison of instruction count between ARM and the smaller RISC-V
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1:27:23Reflect on this comparison of instruction count between ARM and the smaller RISC-V
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1:30:25Chapter 1.3 continued30
1:30:25Chapter 1.3 continued30
1:30:25Chapter 1.3 continued30
1:31:12Consider that RISC-V instructions may have been designed to have a reliable number of clock cycles
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1:31:12Consider that RISC-V instructions may have been designed to have a reliable number of clock cycles
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1:31:12Consider that RISC-V instructions may have been designed to have a reliable number of clock cycles
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1:31:54Chapter 1.3 continued, performance comparison31
1:31:54Chapter 1.3 continued, performance comparison31
1:31:54Chapter 1.3 continued, performance comparison31
1:33:55Wrap it up with a glimpse into the future
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1:33:55Wrap it up with a glimpse into the future
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1:33:55Wrap it up with a glimpse into the future
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