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0:08Recap and set the stage for the day with a mention of the addition of @naked to hula1
0:08Recap and set the stage for the day with a mention of the addition of @naked to hula1
0:08Recap and set the stage for the day with a mention of the addition of @naked to hula1
3:56Review the addition of "register" to hula2
3:56Review the addition of "register" to hula2
3:56Review the addition of "register" to hula2
6:11Show off the hula hello.S asm3
6:11Show off the hula hello.S asm3
6:11Show off the hula hello.S asm3
12:15riskyfive By the way, about porting D to RISC-V. I'm stalled on a GCC bug. Exception support in GCC / glibc has a bug, but people from SiFive are working on it
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12:15riskyfive By the way, about porting D to RISC-V. I'm stalled on a GCC bug. Exception support in GCC / glibc has a bug, but people from SiFive are working on it
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12:15riskyfive By the way, about porting D to RISC-V. I'm stalled on a GCC bug. Exception support in GCC / glibc has a bug, but people from SiFive are working on it
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12:49Thoughts on writing asm and architectural and general portability4
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12:49Thoughts on writing asm and architectural and general portability4
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12:49Thoughts on writing asm and architectural and general portability4
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15:43Jump into the book
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15:43Jump into the book
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15:43Jump into the book
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16:50Compiling an Assignment When an Operand Is in Memory5
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16:50Compiling an Assignment When an Operand Is in Memory5
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16:50Compiling an Assignment When an Operand Is in Memory5
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19:25Our answer to Chapter 2.3 'Compiling an Assignment When an Operand Is in Memory'6
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19:25Our answer to Chapter 2.3 'Compiling an Assignment When an Operand Is in Memory'6
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19:25Our answer to Chapter 2.3 'Compiling an Assignment When an Operand Is in Memory'6
23:09Figure 2.3 Actual RISC-V memory addresses and contents of memory for those doublewords
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23:09Figure 2.3 Actual RISC-V memory addresses and contents of memory for those doublewords
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23:09Figure 2.3 Actual RISC-V memory addresses and contents of memory for those doublewords
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23:54Chapter 2.3 continued8
23:54Chapter 2.3 continued8
23:54Chapter 2.3 continued8
24:30Endianness, with a fun fact: It's a reference to Gulliver's Travels
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24:30Endianness, with a fun fact: It's a reference to Gulliver's Travels
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24:30Endianness, with a fun fact: It's a reference to Gulliver's Travels
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25:56Chapter 2.3 continued9
25:56Chapter 2.3 continued9
25:56Chapter 2.3 continued9
26:39riskyfive We should write things on paper little endian style
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26:39riskyfive We should write things on paper little endian style
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26:39riskyfive We should write things on paper little endian style
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27:07Thoughts on "endianness" in RTL vs LTR languages
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27:07Thoughts on "endianness" in RTL vs LTR languages
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27:07Thoughts on "endianness" in RTL vs LTR languages
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29:20riskyfive Yes, yes, that's the reasoning that'll eventually convince you that we should change to little endian on paper. Let the endianness flow through you. Come to the little side of the force
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29:20riskyfive Yes, yes, that's the reasoning that'll eventually convince you that we should change to little endian on paper. Let the endianness flow through you. Come to the little side of the force
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29:20riskyfive Yes, yes, that's the reasoning that'll eventually convince you that we should change to little endian on paper. Let the endianness flow through you. Come to the little side of the force
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29:48Chapter 2.3 continued10
29:48Chapter 2.3 continued10
29:48Chapter 2.3 continued10
31:21Thoughts on asm syntax, with a mention of Per's chosen syntax for his assembler
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31:21Thoughts on asm syntax, with a mention of Per's chosen syntax for his assembler
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31:21Thoughts on asm syntax, with a mention of Per's chosen syntax for his assembler
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34:52Chapter 2.3 continued11
34:52Chapter 2.3 continued11
34:52Chapter 2.3 continued11
37:12Thoughts on alignment of memory accesses
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37:12Thoughts on alignment of memory accesses
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37:12Thoughts on alignment of memory accesses
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38:35riskyfive Got to go. Good night!
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38:35riskyfive Got to go. Good night!
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38:35riskyfive Got to go. Good night!
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38:44On RISC-V's ability to do unaligned memory accesses
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38:44On RISC-V's ability to do unaligned memory accesses
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38:44On RISC-V's ability to do unaligned memory accesses