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0:08Set the stage for our continuation of the book
0:08Set the stage for our continuation of the book
0:08Set the stage for our continuation of the book
1:00Chapter 2.5 Representing instructions in the Computer1
1:00Chapter 2.5 Representing instructions in the Computer1
1:00Chapter 2.5 Representing instructions in the Computer1
1:58Chapter 2.5 Example 1 - Translating a RISC-V Assembly Instruction into a Machine Instruction2
1:58Chapter 2.5 Example 1 - Translating a RISC-V Assembly Instruction into a Machine Instruction2
1:58Chapter 2.5 Example 1 - Translating a RISC-V Assembly Instruction into a Machine Instruction2
3:11The decimal representation of RISC-V asm `add x9, x20, x21`
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3:11The decimal representation of RISC-V asm `add x9, x20, x21`
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3:11The decimal representation of RISC-V asm `add x9, x20, x21`
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5:29Chapter 2.5 Example 1 continued3
5:29Chapter 2.5 Example 1 continued3
5:29Chapter 2.5 Example 1 continued3
7:34RISC-V Instruction Encoding
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7:34RISC-V Instruction Encoding
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7:34RISC-V Instruction Encoding
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10:03The binary representation of RISC-V asm `add x9, x20, x21`
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10:03The binary representation of RISC-V asm `add x9, x20, x21`
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10:03The binary representation of RISC-V asm `add x9, x20, x21`
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13:05Chapter 2.5 continued, on the instruction format4
13:05Chapter 2.5 continued, on the instruction format4
13:05Chapter 2.5 continued, on the instruction format4
13:32A few words on RISC-V's compressed extension
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13:32A few words on RISC-V's compressed extension
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13:32A few words on RISC-V's compressed extension
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17:20Chapter 2.5 continued, machine language and machine code5
17:20Chapter 2.5 continued, machine language and machine code5
17:20Chapter 2.5 continued, machine language and machine code5
17:30Distinguishing between assembly and machine code
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17:30Distinguishing between assembly and machine code
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17:30Distinguishing between assembly and machine code
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19:50Chapter 2.5 continued, hexadecimal-to-binary conversion6
19:50Chapter 2.5 continued, hexadecimal-to-binary conversion6
19:50Chapter 2.5 continued, hexadecimal-to-binary conversion6
21:47Hexadecimal
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21:47Hexadecimal
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21:47Hexadecimal
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29:12croepha Hello
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29:12croepha Hello
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29:12croepha Hello
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29:15Binary to hexadecimal
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29:15Binary to hexadecimal
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29:15Binary to hexadecimal
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34:40croepha Unrelated: I am of the opinion that humans should have adopted the dozenal (base 12) system instead of base 10
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34:40croepha Unrelated: I am of the opinion that humans should have adopted the dozenal (base 12) system instead of base 10
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34:40croepha Unrelated: I am of the opinion that humans should have adopted the dozenal (base 12) system instead of base 10
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36:02Hexadecimal to decimal conversion
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36:02Hexadecimal to decimal conversion
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36:02Hexadecimal to decimal conversion
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37:22croepha Yeah you can count to 12 on one hand using knuckles and your thumb to point
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37:22croepha Yeah you can count to 12 on one hand using knuckles and your thumb to point
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37:22croepha Yeah you can count to 12 on one hand using knuckles and your thumb to point
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39:47Figure 2.4 - The hexadecimal–binary conversion table7
39:47Figure 2.4 - The hexadecimal–binary conversion table7
39:47Figure 2.4 - The hexadecimal–binary conversion table7
42:09Chapter 2.5 continued, subscripting the numeral system8
42:09Chapter 2.5 continued, subscripting the numeral system8
42:09Chapter 2.5 continued, subscripting the numeral system8
43:46Chapter 2.5 Example 2 - Binary to Hexadecimal and Back9
43:46Chapter 2.5 Example 2 - Binary to Hexadecimal and Back9
43:46Chapter 2.5 Example 2 - Binary to Hexadecimal and Back9
44:52Converting 0xECA86420 to binary
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44:52Converting 0xECA86420 to binary
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44:52Converting 0xECA86420 to binary
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47:46croepha Later, take care
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47:46croepha Later, take care
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47:46croepha Later, take care
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47:54Converting 0001 0011 0101 0111 1001 1011 1101 1111 to hexadecimal
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47:54Converting 0001 0011 0101 0111 1001 1011 1101 1111 to hexadecimal
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47:54Converting 0001 0011 0101 0111 1001 1011 1101 1111 to hexadecimal
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51:34Compare our answer to Chapter 2.5 Example 2 with the book10
51:34Compare our answer to Chapter 2.5 Example 2 with the book10
51:34Compare our answer to Chapter 2.5 Example 2 with the book10
53:33Recommend memorising hexadecimal–binary pairings
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53:33Recommend memorising hexadecimal–binary pairings
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53:33Recommend memorising hexadecimal–binary pairings
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55:55Chapter 2.5 continued, RISC-V Fields11
55:55Chapter 2.5 continued, RISC-V Fields11
55:55Chapter 2.5 continued, RISC-V Fields11
58:38Note that the J-type instructions may no longer exist
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58:38Note that the J-type instructions may no longer exist
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58:38Note that the J-type instructions may no longer exist
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1:00:35Chapter 2.5 continued, instruction formats12
1:00:35Chapter 2.5 continued, instruction formats12
1:00:35Chapter 2.5 continued, instruction formats12
1:05:14Design Principle 3: "Good design demands compromises"
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1:05:14Design Principle 3: "Good design demands compromises"
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1:05:14Design Principle 3: "Good design demands compromises"
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1:08:58Design Principle 2: "Smaller is faster"
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1:08:58Design Principle 2: "Smaller is faster"
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1:08:58Design Principle 2: "Smaller is faster"
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1:14:42Design Principle 1: "Simplicity favours regularity"
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1:14:42Design Principle 1: "Simplicity favours regularity"
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1:14:42Design Principle 1: "Simplicity favours regularity"
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1:16:30Shout-out to RAD Game Tools' employee Mr4thDimention and the quality of his editor 4coder
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1:16:30Shout-out to RAD Game Tools' employee Mr4thDimention and the quality of his editor 4coder
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1:16:30Shout-out to RAD Game Tools' employee Mr4thDimention and the quality of his editor 4coder
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1:20:20Chapter 2.5 continued, the compromises chosen by the RISC-V designers13
1:20:20Chapter 2.5 continued, the compromises chosen by the RISC-V designers13
1:20:20Chapter 2.5 continued, the compromises chosen by the RISC-V designers13
1:24:14The load register instruction from page 7114,15
1:24:14The load register instruction from page 7114,15
1:24:14The load register instruction from page 7114,15
1:28:56Figure 2.5 - RISC-V instruction encoding16
1:28:56Figure 2.5 - RISC-V instruction encoding16
1:28:56Figure 2.5 - RISC-V instruction encoding16
1:32:46Point out the versatility of the opcodes in RISC-V
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1:32:46Point out the versatility of the opcodes in RISC-V
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1:32:46Point out the versatility of the opcodes in RISC-V
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1:34:57Figure 2.5 continued17
1:34:57Figure 2.5 continued17
1:34:57Figure 2.5 continued17
1:36:23A few more words on the versatility and unsimplicity of opcodes
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1:36:23A few more words on the versatility and unsimplicity of opcodes
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1:36:23A few more words on the versatility and unsimplicity of opcodes
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1:38:22Chapter 2.5 Example 3 - Translating RISC-V Assembly Language into Machine Language18
1:38:22Chapter 2.5 Example 3 - Translating RISC-V Assembly Language into Machine Language18
1:38:22Chapter 2.5 Example 3 - Translating RISC-V Assembly Language into Machine Language18
1:39:22Lowering from C to assembly: `A[30] = h + A[30] + 1;`19,20
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1:39:22Lowering from C to assembly: `A[30] = h + A[30] + 1;`19,20
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1:39:22Lowering from C to assembly: `A[30] = h + A[30] + 1;`19,20
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1:50:45Translating our assembly to machine code21,22
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1:50:45Translating our assembly to machine code21,22
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1:50:45Translating our assembly to machine code21,22
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2:23:25Thoughts on viewing RISC-V instructions
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2:23:25Thoughts on viewing RISC-V instructions
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2:23:25Thoughts on viewing RISC-V instructions
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2:31:48Continue translating our assembly to machine code23
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2:31:48Continue translating our assembly to machine code23
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2:31:48Continue translating our assembly to machine code23
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2:44:17Compare our answer to Chapter 2.5 Example 3 with the book24
2:44:17Compare our answer to Chapter 2.5 Example 3 with the book24
2:44:17Compare our answer to Chapter 2.5 Example 3 with the book24
3:09:26A few words on the greater potential for errors in handwritten machine code than C
3:09:26A few words on the greater potential for errors in handwritten machine code than C
3:09:26A few words on the greater potential for errors in handwritten machine code than C
3:14:01Chapter 2.5 Elaborations, on immediate instructions25
3:14:01Chapter 2.5 Elaborations, on immediate instructions25
3:14:01Chapter 2.5 Elaborations, on immediate instructions25
3:15:11Chapter 2.5 Hardware / Software Interface26
3:15:11Chapter 2.5 Hardware / Software Interface26
3:15:11Chapter 2.5 Hardware / Software Interface26
3:15:40Figure 2.6 - RISC-V architecture revealed through Section 2.527
3:15:40Figure 2.6 - RISC-V architecture revealed through Section 2.527
3:15:40Figure 2.6 - RISC-V architecture revealed through Section 2.527
3:18:30Chapter 2.5 The Big Picture28
3:18:30Chapter 2.5 The Big Picture28
3:18:30Chapter 2.5 The Big Picture28
3:19:58Figure 2.7 The stored-program concept29
3:19:58Figure 2.7 The stored-program concept29
3:19:58Figure 2.7 The stored-program concept29
3:21:24Chapter 2.5 Check Yourself30
3:21:24Chapter 2.5 Check Yourself30
3:21:24Chapter 2.5 Check Yourself30
3:24:41That ends section 2.5
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3:24:41That ends section 2.5
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3:24:41That ends section 2.5
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