Jump to Content
Register
Forgot your password?
Third-party login
Log in with Discord

RISCY BUSINESS
Blog
Forums
Episode Guide
twitter
RISCY BUSINESS»Episode Guide
Preface, 1.1-1.3
References ▼
David Patterson and Andrew Waterman (Strawberry Canyon)
RISC-V Reader
[1]0:11[2]1:16[3]4:15
[4]7:47[5]8:09[6]10:42
[8]15:06[9]18:38[11]25:34
[12]26:47[13]30:44[14]32:16
[15]35:56[16]37:38[17]41:35
[18]45:06[19]47:23[20]51:55
[21]59:08[22]1:02:37[23]1:04:12
[26]1:17:35[28]1:22:52[29]1:24:53
[30]1:30:25[31]1:31:54
GitHub
armandofox/​latex2ebook
[7]13:12
RISCY BUSINESS Forums
Useful Links
[10]25:23[25]1:10:00
Molly Rocket
HandmadeCon 2015: Mike Acton
[24]1:06:14
SiFive Forums
[27]1:20:55
Filter mode:
Topics
fabrication
(null topic)
Media
🗪Chat Comment
🖮Programming🟉
📖Research
🗩Speech
🖌Whiteboard
🎭
🏟
🔗
Link to: current timestamp
Credits
Host
Neo Ar
Indexer
Matt Mascarenhas
?
?

Keyboard Navigation

Global Keys

[, < / ], > Jump to previous / next episode
W, K, P / S, J, N Jump to previous / next marker
t / T Toggle theatre / SUPERtheatre mode
V Revert filter to original state Y Select link (requires manual Ctrl-c)

Menu toggling

q Quotes r References f Filter y Link c Credits

In-Menu Movement

a
w
s
d
h j k l
←
↑
↓
→

Quotes and References Menus

Enter Jump to timecode

Quotes, References and Credits Menus

o Open URL (in new tab)

Filter Menu

x, Space Toggle category and focus next
X, ShiftSpace Toggle category and focus previous
v Invert topics / media as per focus

Filter and Link Menus

z Toggle filter / linking mode

Credits Menu

Enter Open URL (in new tab)
•
Welcome to Risc-V Book Club
•
0:11Introduce the RISC-V Reader1
🗩
0:11Introduce the RISC-V Reader1
🗩
0:11Introduce the RISC-V Reader1
🗩
1:16The back cover2
📖
1:16The back cover2
📖
1:16The back cover2
📖
4:15Pre-preface3
📖
4:15Pre-preface3
📖
4:15Pre-preface3
📖
7:29dannyfritz ped a gah gee
🗪
7:29dannyfritz ped a gah gee
🗪
7:29dannyfritz ped a gah gee
🗪
7:47Pre-preface continued4
📖
7:47Pre-preface continued4
📖
7:47Pre-preface continued4
📖
8:00dannyfritz ped a gah jee
🗪
8:00dannyfritz ped a gah jee
🗪
8:00dannyfritz ped a gah jee
🗪
8:09Pre-preface continued5
📖
8:09Pre-preface continued5
📖
8:09Pre-preface continued5
📖
10:42Background from the publisher6
📖
10:42Background from the publisher6
📖
10:42Background from the publisher6
📖
13:12Check out the GitHub repository7
📖
13:12Check out the GitHub repository7
📖
13:12Check out the GitHub repository7
📖
15:06Dedication8
📖
15:06Dedication8
📖
15:06Dedication8
📖
18:38Preface9
📖
18:38Preface9
📖
18:38Preface9
📖
25:23Plug links.riscy.tv10
25:23Plug links.riscy.tv10
25:23Plug links.riscy.tv10
25:34Preface continued11
📖
25:34Preface continued11
📖
25:34Preface continued11
📖
26:47History of this book12
📖
26:47History of this book12
📖
26:47History of this book12
📖
30:44Chapter 1 - Why RISC-V?13
📖
30:44Chapter 1 - Why RISC-V?13
📖
30:44Chapter 1 - Why RISC-V?13
📖
32:16Chapter 1.1 - Introduction14
📖
32:16Chapter 1.1 - Introduction14
📖
32:16Chapter 1.1 - Introduction14
📖
33:29A few words on deep learning
🗩
33:29A few words on deep learning
🗩
33:29A few words on deep learning
🗩
35:56Chapter 1.1 continued15
📖
35:56Chapter 1.1 continued15
📖
35:56Chapter 1.1 continued15
📖
37:38Figure 1.1 - Members of the RISC-V foundation16
📖
37:38Figure 1.1 - Members of the RISC-V foundation16
📖
37:38Figure 1.1 - Members of the RISC-V foundation16
📖
41:35Figure 1.2 - Growth of the x86 instruction set over its lifetime17
📖
41:35Figure 1.2 - Growth of the x86 instruction set over its lifetime17
📖
41:35Figure 1.2 - Growth of the x86 instruction set over its lifetime17
📖
45:06Figure 1.3 - A description of the x86-32 ASCII adjust after addition instruction18
📖
45:06Figure 1.3 - A description of the x86-32 ASCII adjust after addition instruction18
📖
45:06Figure 1.3 - A description of the x86-32 ASCII adjust after addition instruction18
📖
47:23Chapter 1.2 - Modular vs Incremental ISAs19
📖
47:23Chapter 1.2 - Modular vs Incremental ISAs19
📖
47:23Chapter 1.2 - Modular vs Incremental ISAs19
📖
51:09Reflect on the analogy of a meal becoming a banquet to an ISA growing incrementally
🗩
51:09Reflect on the analogy of a meal becoming a banquet to an ISA growing incrementally
🗩
51:09Reflect on the analogy of a meal becoming a banquet to an ISA growing incrementally
🗩
51:55Chapter 1.2 continued20
📖
51:55Chapter 1.2 continued20
📖
51:55Chapter 1.2 continued20
📖
56:27dannyfritz SSE SSE2 SSE3
🗪
56:27dannyfritz SSE SSE2 SSE3
🗪
56:27dannyfritz SSE SSE2 SSE3
🗪
57:18dannyfritz Not sure, I feel like SSE3 requires SSE2 and SSE
🗪
57:18dannyfritz Not sure, I feel like SSE3 requires SSE2 and SSE
🗪
57:18dannyfritz Not sure, I feel like SSE3 requires SSE2 and SSE
🗪
58:47dannyfritz Oh, like ARB in OpenGL. Interesting
🗪
58:47dannyfritz Oh, like ARB in OpenGL. Interesting
🗪
58:47dannyfritz Oh, like ARB in OpenGL. Interesting
🗪
59:08Chapter 1.3 - ISA Design 10121
📖
59:08Chapter 1.3 - ISA Design 10121
📖
59:08Chapter 1.3 - ISA Design 10121
📖
1:02:37Figure 1.4 - An 8″ diameter wafer of a RISC-V die designed by SiFive22
📖
1:02:37Figure 1.4 - An 8″ diameter wafer of a RISC-V die designed by SiFive22
📖
1:02:37Figure 1.4 - An 8″ diameter wafer of a RISC-V die designed by SiFive22
📖
1:04:12Chapter 1.3 continued23
📖
1:04:12Chapter 1.3 continued23
📖
1:04:12Chapter 1.3 continued23
📖
1:06:14Recall Mike Acton's recommendation from HandmadeCon 201524 to read x86 manuals
🗩
1:06:14Recall Mike Acton's recommendation from HandmadeCon 201524 to read x86 manuals
🗩
1:06:14Recall Mike Acton's recommendation from HandmadeCon 201524 to read x86 manuals
🗩
1:09:39dannyfritz Does that include docs for extensions?
🗪
1:09:39dannyfritz Does that include docs for extensions?
🗪
1:09:39dannyfritz Does that include docs for extensions?
🗪
1:10:00Show the HiFive1 documentation25
📖
1:10:00Show the HiFive1 documentation25
📖
1:10:00Show the HiFive1 documentation25
📖
1:16:02Compare the quantities of documentation for RISC-V and x86
🗩
1:16:02Compare the quantities of documentation for RISC-V and x86
🗩
1:16:02Compare the quantities of documentation for RISC-V and x86
🗩
1:17:35Chapter 1.3 continued26
📖
1:17:35Chapter 1.3 continued26
📖
1:17:35Chapter 1.3 continued26
📖
1:20:55dannyfritz Do RISC-V instructions always operate in 1 cycle?27
🗪
1:20:55dannyfritz Do RISC-V instructions always operate in 1 cycle?27
🗪
1:20:55dannyfritz Do RISC-V instructions always operate in 1 cycle?27
🗪
1:22:52Chapter 1.3 continued28
📖
1:22:52Chapter 1.3 continued28
📖
1:22:52Chapter 1.3 continued28
📖
1:23:38Find the running time equation on the blackboard
🖌
1:23:38Find the running time equation on the blackboard
🖌
1:23:38Find the running time equation on the blackboard
🖌
1:24:53Chapter 1.3 continued, on cycles per instruction29
📖
1:24:53Chapter 1.3 continued, on cycles per instruction29
📖
1:24:53Chapter 1.3 continued, on cycles per instruction29
📖
1:27:23Reflect on this comparison of instruction count between ARM and the smaller RISC-V
🗩
1:27:23Reflect on this comparison of instruction count between ARM and the smaller RISC-V
🗩
1:27:23Reflect on this comparison of instruction count between ARM and the smaller RISC-V
🗩
1:30:25Chapter 1.3 continued30
📖
1:30:25Chapter 1.3 continued30
📖
1:30:25Chapter 1.3 continued30
📖
1:31:12Consider that RISC-V instructions may have been designed to have a reliable number of clock cycles
🗩
1:31:12Consider that RISC-V instructions may have been designed to have a reliable number of clock cycles
🗩
1:31:12Consider that RISC-V instructions may have been designed to have a reliable number of clock cycles
🗩
1:31:54Chapter 1.3 continued, performance comparison31
📖
1:31:54Chapter 1.3 continued, performance comparison31
📖
1:31:54Chapter 1.3 continued, performance comparison31
📖
1:33:55Wrap it up with a glimpse into the future
🗩
1:33:55Wrap it up with a glimpse into the future
🗩
1:33:55Wrap it up with a glimpse into the future
🗩