Jump to Content
Register Log in

RISCY BUSINESS
Blog
Forums
Episode Guide
twitter
We are currently in the process of converting the website to the new design. Some pages, like this one, are still broken. We appreciate your patience.
RISCY BUSINESS»Episode Guide
PRCI
References ▼
SiFive Developers
E3 Coreplex Manual
[1]0:45[2]2:57
SiFive Developers
Platform Reference Manual
[3]9:01[4]16:35[5]20:29
[6]22:47[7]23:40[8]24:47
[10]31:52[11]39:20[12]43:18
[13]50:00[14]51:15[15]51:55
Wikipedia
Phase-locked loop
[9]24:47
RISC-V
Draft Privileged ISA Specification v1.9.1
[16]1:00:34
RISC-V
User-Level ISA Specification v2.1
[17]1:04:29
Filter mode:
Topics
asm
hardware
performance
(null topic)
Media
🗪Chat Comment
🖮Programming🟉
📖Research
🖌Whiteboard
🎭
🏟
🔗
Link to: current timestamp
Credits
Host
Neo Ar
Indexer
Matt Mascarenhas
?
?

Keyboard Navigation

Global Keys

[, < / ], > Jump to previous / next episode
W, K, P / S, J, N Jump to previous / next marker
t / T Toggle theatre / SUPERtheatre mode
V Revert filter to original state Y Select link (requires manual Ctrl-c)

Menu toggling

q Quotes r References f Filter y Link c Credits

In-Menu Movement

a
w
s
d
h j k l
←
↑
↓
→

Quotes and References Menus

Enter Jump to timecode

Quotes, References and Credits Menus

o Open URL (in new tab)

Filter Menu

x, Space Toggle category and focus next
X, ShiftSpace Toggle category and focus previous
v Invert topics / media as per focus

Filter and Link Menus

z Toggle filter / linking mode

Credits Menu

Enter Open URL (in new tab)
0:07Recap and set the stage for the day
0:07Recap and set the stage for the day
0:07Recap and set the stage for the day
0:45Read about E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers1
📖
0:45Read about E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers1
📖
0:45Read about E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers1
📖
2:57Marry up the PRCI_REG macro and the PRCI register offsets from the code with the documentation2
📖
2:57Marry up the PRCI_REG macro and the PRCI register offsets from the code with the documentation2
📖
2:57Marry up the PRCI_REG macro and the PRCI register offsets from the code with the documentation2
📖
5:22Hunt for further documentation on the PRCI
5:22Hunt for further documentation on the PRCI
5:22Hunt for further documentation on the PRCI
9:01Read about E300 Clock Generation3
📖
9:01Read about E300 Clock Generation3
📖
9:01Read about E300 Clock Generation3
📖
14:04A few thoughts on ring oscillator and trim
14:04A few thoughts on ring oscillator and trim
14:04A few thoughts on ring oscillator and trim
15:36riskyfive Just a chain of not gates
🗪
15:36riskyfive Just a chain of not gates
🗪
15:36riskyfive Just a chain of not gates
🗪
15:40Continued thoughts on how the trim value works
15:40Continued thoughts on how the trim value works
15:40Continued thoughts on how the trim value works
16:35Continue reading about the Internal Trimmable Programmable 72 MHz Oscillator (HFROSC)4
📖
16:35Continue reading about the Internal Trimmable Programmable 72 MHz Oscillator (HFROSC)4
📖
16:35Continue reading about the Internal Trimmable Programmable 72 MHz Oscillator (HFROSC)4
📖
20:29Read about External 16 MHz Crystal Oscilllator (HFXOSC)5
📖
20:29Read about External 16 MHz Crystal Oscilllator (HFXOSC)5
📖
20:29Read about External 16 MHz Crystal Oscilllator (HFXOSC)5
📖
22:35riskyfive ESR: equivalent series resistance
🗪
22:35riskyfive ESR: equivalent series resistance
🗪
22:35riskyfive ESR: equivalent series resistance
🗪
22:47Continue reading about the HFXOSC6
📖
22:47Continue reading about the HFXOSC6
📖
22:47Continue reading about the HFXOSC6
📖
23:31riskyfive Voltage-controlled oscillator
🗪
23:31riskyfive Voltage-controlled oscillator
🗪
23:31riskyfive Voltage-controlled oscillator
🗪
23:40Continue reading about HFXOSC7
📖
23:40Continue reading about HFXOSC7
📖
23:40Continue reading about HFXOSC7
📖
24:47Read about Internal High-Frequency PLL (HFPLL)8 and Phase-locked loop9
📖
24:47Read about Internal High-Frequency PLL (HFPLL)8 and Phase-locked loop9
📖
24:47Read about Internal High-Frequency PLL (HFPLL)8 and Phase-locked loop9
📖
27:59Determine to add to the plan
🖌
27:59Determine to add to the plan
🖌
27:59Determine to add to the plan
🖌
30:17riskyfive i.e. an assembler ;)
🗪
30:17riskyfive i.e. an assembler ;)
🗪
30:17riskyfive i.e. an assembler ;)
🗪
30:31Add "compare a demo's asm to expected", "study the hardware implementation" and "write software" to the plan
🖌
30:31Add "compare a demo's asm to expected", "study the hardware implementation" and "write software" to the plan
🖌
30:31Add "compare a demo's asm to expected", "study the hardware implementation" and "write software" to the plan
🖌
31:52Continue reading about HFPLL10
📖
31:52Continue reading about HFPLL10
📖
31:52Continue reading about HFPLL10
📖
35:18A few thoughts on how the PLL relates to the marketed clock rate of the HiFive1
🖌
35:18A few thoughts on how the PLL relates to the marketed clock rate of the HiFive1
🖌
35:18A few thoughts on how the PLL relates to the marketed clock rate of the HiFive1
🖌
37:04riskyfive The PPL generates the higher clock rates from the crystal
🗪
37:04riskyfive The PPL generates the higher clock rates from the crystal
🗪
37:04riskyfive The PPL generates the higher clock rates from the crystal
🗪
37:59riskyfive Probably not within spec
🗪
37:59riskyfive Probably not within spec
🗪
37:59riskyfive Probably not within spec
🗪
38:25Consider overclocking a HiFive1 (not our main one, though!)
38:25Consider overclocking a HiFive1 (not our main one, though!)
38:25Consider overclocking a HiFive1 (not our main one, though!)
39:20Continue reading about HFPLL11
📖
39:20Continue reading about HFPLL11
📖
39:20Continue reading about HFPLL11
📖
42:23riskyfive When they say 0 is not supported I'm imagining it's because the core doesn't run that quickly, not because that divider wouldn't work
🗪
42:23riskyfive When they say 0 is not supported I'm imagining it's because the core doesn't run that quickly, not because that divider wouldn't work
🗪
42:23riskyfive When they say 0 is not supported I'm imagining it's because the core doesn't run that quickly, not because that divider wouldn't work
🗪
43:18Continue reading about HFPLL12
📖
43:18Continue reading about HFPLL12
📖
43:18Continue reading about HFPLL12
📖
49:49Read about PLL
49:49Read about PLL
49:49Read about PLL
49:54riskyfive VDD and VSS are power pins
🗪
49:54riskyfive VDD and VSS are power pins
🗪
49:54riskyfive VDD and VSS are power pins
🗪
50:00Read about PLL Output Divider13
📖
50:00Read about PLL Output Divider13
📖
50:00Read about PLL Output Divider13
📖
51:15Read about Internal Low-Frequency Oscillator (LFRCOSC)14
📖
51:15Read about Internal Low-Frequency Oscillator (LFRCOSC)14
📖
51:15Read about Internal Low-Frequency Oscillator (LFRCOSC)14
📖
51:55Read about External 32.768 kHz Low-Frequency Crystal Oscillator (LFXOSC)15
📖
51:55Read about External 32.768 kHz Low-Frequency Crystal Oscillator (LFXOSC)15
📖
51:55Read about External 32.768 kHz Low-Frequency Crystal Oscillator (LFXOSC)15
📖
52:39Determine that we fully understand the opening code of led_fade.c and consult the PLL_* macros
52:39Determine that we fully understand the opening code of led_fade.c and consult the PLL_* macros
52:39Determine that we fully understand the opening code of led_fade.c and consult the PLL_* macros
55:19Cross off "PRCI" and move on to "Other Demos"
🖌
55:19Cross off "PRCI" and move on to "Other Demos"
🖌
55:19Cross off "PRCI" and move on to "Other Demos"
🖌
56:34Embark on studying performance_counters.c
📖
56:34Embark on studying performance_counters.c
📖
56:34Embark on studying performance_counters.c
📖
1:00:34Read 3.1.15 Hardware Performance Monitor16
1:00:34Read 3.1.15 Hardware Performance Monitor16
1:00:34Read 3.1.15 Hardware Performance Monitor16
1:03:34Continue reading the rdmcycle() macro
📖
1:03:34Continue reading the rdmcycle() macro
📖
1:03:34Continue reading the rdmcycle() macro
📖
1:04:29Read about BNE in 2.5 Control Transfer Instructions and CSRRS in 2.8 Control and Status Register Instructions17
📖
1:04:29Read about BNE in 2.5 Control Transfer Instructions and CSRRS in 2.8 Control and Status Register Instructions17
📖
1:04:29Read about BNE in 2.5 Control Transfer Instructions and CSRRS in 2.8 Control and Status Register Instructions17
📖
1:09:50Summarise how rdmcycle() is checking for rollover into the high half of the register
1:09:50Summarise how rdmcycle() is checking for rollover into the high half of the register
1:09:50Summarise how rdmcycle() is checking for rollover into the high half of the register
1:10:53riskyfive Not rollover completely, only increment in the part of mcycleh
🗪
1:10:53riskyfive Not rollover completely, only increment in the part of mcycleh
🗪
1:10:53riskyfive Not rollover completely, only increment in the part of mcycleh
🗪
1:11:32Wonder if the 1b in rdmcycle() means 1 in binary
1:11:32Wonder if the 1b in rdmcycle() means 1 in binary
1:11:32Wonder if the 1b in rdmcycle() means 1 in binary
1:12:26We are out of time for today
1:12:26We are out of time for today
1:12:26We are out of time for today
1:12:39riskyfive Skip over what?
🗪
1:12:39riskyfive Skip over what?
🗪
1:12:39riskyfive Skip over what?
🗪
1:13:39Determine to investigate deeper in the next episode
1:13:39Determine to investigate deeper in the next episode
1:13:39Determine to investigate deeper in the next episode