PRCI
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0:07Recap and set the stage for the day
0:07Recap and set the stage for the day
0:07Recap and set the stage for the day
0:45Read about E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers1
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0:45Read about E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers1
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0:45Read about E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers1
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2:57Marry up the PRCI_REG macro and the PRCI register offsets from the code with the documentation2
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2:57Marry up the PRCI_REG macro and the PRCI register offsets from the code with the documentation2
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2:57Marry up the PRCI_REG macro and the PRCI register offsets from the code with the documentation2
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5:22Hunt for further documentation on the PRCI
5:22Hunt for further documentation on the PRCI
5:22Hunt for further documentation on the PRCI
9:01Read about E300 Clock Generation3
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9:01Read about E300 Clock Generation3
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9:01Read about E300 Clock Generation3
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14:04A few thoughts on ring oscillator and trim
14:04A few thoughts on ring oscillator and trim
14:04A few thoughts on ring oscillator and trim
15:36riskyfive Just a chain of not gates
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15:36riskyfive Just a chain of not gates
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15:36riskyfive Just a chain of not gates
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15:40Continued thoughts on how the trim value works
15:40Continued thoughts on how the trim value works
15:40Continued thoughts on how the trim value works
16:35Continue reading about the Internal Trimmable Programmable 72 MHz Oscillator (HFROSC)4
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16:35Continue reading about the Internal Trimmable Programmable 72 MHz Oscillator (HFROSC)4
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16:35Continue reading about the Internal Trimmable Programmable 72 MHz Oscillator (HFROSC)4
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20:29Read about External 16 MHz Crystal Oscilllator (HFXOSC)5
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20:29Read about External 16 MHz Crystal Oscilllator (HFXOSC)5
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20:29Read about External 16 MHz Crystal Oscilllator (HFXOSC)5
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22:35riskyfive ESR: equivalent series resistance
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22:35riskyfive ESR: equivalent series resistance
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22:35riskyfive ESR: equivalent series resistance
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22:47Continue reading about the HFXOSC6
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22:47Continue reading about the HFXOSC6
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22:47Continue reading about the HFXOSC6
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23:31riskyfive Voltage-controlled oscillator
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23:31riskyfive Voltage-controlled oscillator
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23:31riskyfive Voltage-controlled oscillator
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23:40Continue reading about HFXOSC7
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23:40Continue reading about HFXOSC7
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23:40Continue reading about HFXOSC7
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24:47Read about Internal High-Frequency PLL (HFPLL)8 and Phase-locked loop9
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24:47Read about Internal High-Frequency PLL (HFPLL)8 and Phase-locked loop9
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24:47Read about Internal High-Frequency PLL (HFPLL)8 and Phase-locked loop9
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27:59Determine to add to the plan
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27:59Determine to add to the plan
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27:59Determine to add to the plan
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30:17riskyfive i.e. an assembler ;)
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30:17riskyfive i.e. an assembler ;)
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30:17riskyfive i.e. an assembler ;)
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30:31Add "compare a demo's asm to expected", "study the hardware implementation" and "write software" to the plan
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30:31Add "compare a demo's asm to expected", "study the hardware implementation" and "write software" to the plan
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30:31Add "compare a demo's asm to expected", "study the hardware implementation" and "write software" to the plan
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31:52Continue reading about HFPLL10
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31:52Continue reading about HFPLL10
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31:52Continue reading about HFPLL10
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35:18A few thoughts on how the PLL relates to the marketed clock rate of the HiFive1
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35:18A few thoughts on how the PLL relates to the marketed clock rate of the HiFive1
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35:18A few thoughts on how the PLL relates to the marketed clock rate of the HiFive1
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37:04riskyfive The PPL generates the higher clock rates from the crystal
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37:04riskyfive The PPL generates the higher clock rates from the crystal
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37:04riskyfive The PPL generates the higher clock rates from the crystal
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37:59riskyfive Probably not within spec
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37:59riskyfive Probably not within spec
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37:59riskyfive Probably not within spec
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38:25Consider overclocking a HiFive1 (not our main one, though!)
38:25Consider overclocking a HiFive1 (not our main one, though!)
38:25Consider overclocking a HiFive1 (not our main one, though!)
39:20Continue reading about HFPLL11
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39:20Continue reading about HFPLL11
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39:20Continue reading about HFPLL11
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42:23riskyfive When they say 0 is not supported I'm imagining it's because the core doesn't run that quickly, not because that divider wouldn't work
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42:23riskyfive When they say 0 is not supported I'm imagining it's because the core doesn't run that quickly, not because that divider wouldn't work
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42:23riskyfive When they say 0 is not supported I'm imagining it's because the core doesn't run that quickly, not because that divider wouldn't work
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43:18Continue reading about HFPLL12
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43:18Continue reading about HFPLL12
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43:18Continue reading about HFPLL12
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49:49Read about PLL
49:49Read about PLL
49:49Read about PLL
49:54riskyfive VDD and VSS are power pins
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49:54riskyfive VDD and VSS are power pins
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49:54riskyfive VDD and VSS are power pins
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50:00Read about PLL Output Divider13
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50:00Read about PLL Output Divider13
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50:00Read about PLL Output Divider13
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51:15Read about Internal Low-Frequency Oscillator (LFRCOSC)14
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51:15Read about Internal Low-Frequency Oscillator (LFRCOSC)14
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51:15Read about Internal Low-Frequency Oscillator (LFRCOSC)14
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51:55Read about External 32.768 kHz Low-Frequency Crystal Oscillator (LFXOSC)15
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51:55Read about External 32.768 kHz Low-Frequency Crystal Oscillator (LFXOSC)15
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51:55Read about External 32.768 kHz Low-Frequency Crystal Oscillator (LFXOSC)15
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52:39Determine that we fully understand the opening code of led_fade.c and consult the PLL_* macros
52:39Determine that we fully understand the opening code of led_fade.c and consult the PLL_* macros
52:39Determine that we fully understand the opening code of led_fade.c and consult the PLL_* macros
55:19Cross off "PRCI" and move on to "Other Demos"
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55:19Cross off "PRCI" and move on to "Other Demos"
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55:19Cross off "PRCI" and move on to "Other Demos"
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56:34Embark on studying performance_counters.c
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56:34Embark on studying performance_counters.c
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56:34Embark on studying performance_counters.c
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1:00:34Read 3.1.15 Hardware Performance Monitor16
1:00:34Read 3.1.15 Hardware Performance Monitor16
1:00:34Read 3.1.15 Hardware Performance Monitor16
1:03:34Continue reading the rdmcycle() macro
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1:03:34Continue reading the rdmcycle() macro
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1:03:34Continue reading the rdmcycle() macro
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1:04:29Read about BNE in 2.5 Control Transfer Instructions and CSRRS in 2.8 Control and Status Register Instructions17
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1:04:29Read about BNE in 2.5 Control Transfer Instructions and CSRRS in 2.8 Control and Status Register Instructions17
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1:04:29Read about BNE in 2.5 Control Transfer Instructions and CSRRS in 2.8 Control and Status Register Instructions17
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1:09:50Summarise how rdmcycle() is checking for rollover into the high half of the register
1:09:50Summarise how rdmcycle() is checking for rollover into the high half of the register
1:09:50Summarise how rdmcycle() is checking for rollover into the high half of the register
1:10:53riskyfive Not rollover completely, only increment in the part of mcycleh
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1:10:53riskyfive Not rollover completely, only increment in the part of mcycleh
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1:10:53riskyfive Not rollover completely, only increment in the part of mcycleh
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1:11:32Wonder if the 1b in rdmcycle() means 1 in binary
1:11:32Wonder if the 1b in rdmcycle() means 1 in binary
1:11:32Wonder if the 1b in rdmcycle() means 1 in binary
1:12:26We are out of time for today
1:12:26We are out of time for today
1:12:26We are out of time for today
1:12:39riskyfive Skip over what?
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1:12:39riskyfive Skip over what?
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1:12:39riskyfive Skip over what?
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1:13:39Determine to investigate deeper in the next episode
1:13:39Determine to investigate deeper in the next episode
1:13:39Determine to investigate deeper in the next episode