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RISCY BUSINESS»Episode Guide
pwm_speed_test refresher & handle_trap
References ▼
SiFive Developers
SiFive HiFive1 Getting Started Guide
[1]8:36
RISC-V
Draft Privileged ISA Specification v1.9.1
[2]23:33[5]33:32[7]41:02
[8]45:46[10]54:41
Wikipedia
Xen
[3]23:33
Wikipedia
Qubes OS
[4]23:33
RISC-V Foundation
Software Status
[6]33:32
Twitter
@hmn_riscy: I'm going to be trying the following stream schedule (Mon-Fri): 09:00-14:00 CST: Programming 14:00-15:00 CST: RISCY BUSINESS 15:00-17:00 CST: Games
[9]50:57
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Neo Ar
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0:08Recap and set the stage for the day
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0:08Recap and set the stage for the day
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0:08Recap and set the stage for the day
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0:46Reacquaint ourselves with pwm_speed_test.c
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0:46Reacquaint ourselves with pwm_speed_test.c
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0:46Reacquaint ourselves with pwm_speed_test.c
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8:36Compile pwm_speed_test1 and recall that the program didn't do what we want
8:36Compile pwm_speed_test1 and recall that the program didn't do what we want
8:36Compile pwm_speed_test1 and recall that the program didn't do what we want
11:32Consult the annotations for days 049 and 050 to see how we got where we did
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11:32Consult the annotations for days 049 and 050 to see how we got where we did
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11:32Consult the annotations for days 049 and 050 to see how we got where we did
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20:30Learn how mei_isr() is setup in global_interrupts.c
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20:30Learn how mei_isr() is setup in global_interrupts.c
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20:30Learn how mei_isr() is setup in global_interrupts.c
📖
23:33Read 3.1.12 - Machine Trap Delegation Registers (medeleg and mideleg)2 with mentions of hypervisor mode as used in Xen3 and Qubes OS4
📖
23:33Read 3.1.12 - Machine Trap Delegation Registers (medeleg and mideleg)2 with mentions of hypervisor mode as used in Xen3 and Qubes OS4
📖
23:33Read 3.1.12 - Machine Trap Delegation Registers (medeleg and mideleg)2 with mentions of hypervisor mode as used in Xen3 and Qubes OS4
📖
33:32Continue to read 3.1.125 with a mention of RISC-V based real-time software6
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33:32Continue to read 3.1.125 with a mention of RISC-V based real-time software6
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33:32Continue to read 3.1.125 with a mention of RISC-V based real-time software6
📖
37:21Scan through the other documentation for chip specifications of privilege modes
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37:21Scan through the other documentation for chip specifications of privilege modes
📖
37:21Scan through the other documentation for chip specifications of privilege modes
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41:02Continue to read 3.1.12 about trap delegation7
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41:02Continue to read 3.1.12 about trap delegation7
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41:02Continue to read 3.1.12 about trap delegation7
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45:46Read 3.1.11 - Machine Trap-Vector Base-Address Register (mtvec)8 with a moment of realisation as to why we do .align 2
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45:46Read 3.1.11 - Machine Trap-Vector Base-Address Register (mtvec)8 with a moment of realisation as to why we do .align 2
📖
45:46Read 3.1.11 - Machine Trap-Vector Base-Address Register (mtvec)8 with a moment of realisation as to why we do .align 2
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50:57Show the RISC-V Reader and plug the stream schedule9
🗩
50:57Show the RISC-V Reader and plug the stream schedule9
🗩
50:57Show the RISC-V Reader and plug the stream schedule9
🗩
54:41Continue to read 3.1.11 on implementation-specific trap handlers10
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54:41Continue to read 3.1.11 on implementation-specific trap handlers10
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54:41Continue to read 3.1.11 on implementation-specific trap handlers10
📖
58:46Study the trap handling code in the Freedom E SDK and Coreplex IP E31 Arty
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58:46Study the trap handling code in the Freedom E SDK and Coreplex IP E31 Arty
📖
58:46Study the trap handling code in the Freedom E SDK and Coreplex IP E31 Arty
📖
1:04:45pwm_speed_test.c: Call write_csr() and introduce handle_trap()
1:04:45pwm_speed_test.c: Call write_csr() and introduce handle_trap()
1:04:45pwm_speed_test.c: Call write_csr() and introduce handle_trap()
1:11:50Commit "Day 54"
🗹
1:11:50Commit "Day 54"
🗹
1:11:50Commit "Day 54"
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1:13:08End it here
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1:13:08End it here
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1:13:08End it here
🗩