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RISCY BUSINESS»Episode Guide
2.1-2.3
References ▼
David Patterson and Andrew Waterman (Strawberry Canyon)
RISC-V Reader
[1]0:31[2]1:29[3]7:24
[4]7:38[5]11:31[6]30:54
[7]43:21[9]48:25[10]49:44
[11]51:03[12]52:47[13]54:03
[14]58:48[15]1:00:11[16]1:00:39
[17]1:02:41[18]1:03:39
RISCY BUSINESS
Annotated Episode Guide
[8]45:43
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0:01Welcome to the stream
🗩
0:01Welcome to the stream
🗩
0:01Welcome to the stream
🗩
0:31Chapter 2 - RV32I: RISC-V Base Integer ISA1
0:31Chapter 2 - RV32I: RISC-V Base Integer ISA1
0:31Chapter 2 - RV32I: RISC-V Base Integer ISA1
1:29Chapter 2.1 - Introduction2
1:29Chapter 2.1 - Introduction2
1:29Chapter 2.1 - Introduction2
2:30Map the tablet
🗹
2:30Map the tablet
🗹
2:30Map the tablet
🗹
3:02The set notation used in the book to describe the ISA
🖌
3:02The set notation used in the book to describe the ISA
🖌
3:02The set notation used in the book to describe the ISA
🖌
7:24Chapter 2.1 continued3
7:24Chapter 2.1 continued3
7:24Chapter 2.1 continued3
7:38Chapter 2.2 - RV32I Instruction Formats4
7:38Chapter 2.2 - RV32I Instruction Formats4
7:38Chapter 2.2 - RV32I Instruction Formats4
11:31Figure 2.1 - Diagram of the RV32I instructions5
11:31Figure 2.1 - Diagram of the RV32I instructions5
11:31Figure 2.1 - Diagram of the RV32I instructions5
18:06Diagram of the RV32I instructions
🖌
18:06Diagram of the RV32I instructions
🖌
18:06Diagram of the RV32I instructions
🖌
30:54Figure 2.2 - RISC-V instruction formats6
30:54Figure 2.2 - RISC-V instruction formats6
30:54Figure 2.2 - RISC-V instruction formats6
34:10Add B-type to our RISC-V instruction formats diagram
🖌
34:10Add B-type to our RISC-V instruction formats diagram
🖌
34:10Add B-type to our RISC-V instruction formats diagram
🖌
37:43Explain the RISC-V instruction formats diagram
🖌
37:43Explain the RISC-V instruction formats diagram
🖌
37:43Explain the RISC-V instruction formats diagram
🖌
40:09Add J-type to our RISC-V instruction formats diagram
🖌
40:09Add J-type to our RISC-V instruction formats diagram
🖌
40:09Add J-type to our RISC-V instruction formats diagram
🖌
42:25Explain immediates and their encoding
🗩
42:25Explain immediates and their encoding
🗩
42:25Explain immediates and their encoding
🗩
43:21Figure 2.3 - RV32I opcode map7
43:21Figure 2.3 - RV32I opcode map7
43:21Figure 2.3 - RV32I opcode map7
45:43Search the annotated episode guide for "instruction encoding"8
45:43Search the annotated episode guide for "instruction encoding"8
45:43Search the annotated episode guide for "instruction encoding"8
48:25Figure 2.3 continued, with thoughts on funct39
48:25Figure 2.3 continued, with thoughts on funct39
48:25Figure 2.3 continued, with thoughts on funct39
49:41snail7777777 Hey, bud
🗪
49:41snail7777777 Hey, bud
🗪
49:41snail7777777 Hey, bud
🗪
49:44Continued thoughts on funct310
49:44Continued thoughts on funct310
49:44Continued thoughts on funct310
51:03Chapter 2.2 continued, Elaboration: B- and J-type formats11
51:03Chapter 2.2 continued, Elaboration: B- and J-type formats11
51:03Chapter 2.2 continued, Elaboration: B- and J-type formats11
52:47Chapter 2.2 continued, Aside: Sign-extended immediates even help logical instructions12
52:47Chapter 2.2 continued, Aside: Sign-extended immediates even help logical instructions12
52:47Chapter 2.2 continued, Aside: Sign-extended immediates even help logical instructions12
54:03Chapter 2.2 continued, illegal instructions and leaving room for extensions13
54:03Chapter 2.2 continued, illegal instructions and leaving room for extensions13
54:03Chapter 2.2 continued, illegal instructions and leaving room for extensions13
56:46Thoughts on the carefully arranged immediates
🗩
56:46Thoughts on the carefully arranged immediates
🗩
56:46Thoughts on the carefully arranged immediates
🗩
58:48Chapter 2.2 continued, enabling hardware simplicity14
58:48Chapter 2.2 continued, enabling hardware simplicity14
58:48Chapter 2.2 continued, enabling hardware simplicity14
1:00:11Chapter 2.2 continued, Aside: RISC-V implementations all use the same opcode for the optional extensions15
1:00:11Chapter 2.2 continued, Aside: RISC-V implementations all use the same opcode for the optional extensions15
1:00:11Chapter 2.2 continued, Aside: RISC-V implementations all use the same opcode for the optional extensions15
1:00:39Chapter 2.2 continued, the ARM-32 12-bit immediate field16
1:00:39Chapter 2.2 continued, the ARM-32 12-bit immediate field16
1:00:39Chapter 2.2 continued, the ARM-32 12-bit immediate field16
1:02:41Chapter 2.2 continued, Elaboration: Out-of-order processors17
1:02:41Chapter 2.2 continued, Elaboration: Out-of-order processors17
1:02:41Chapter 2.2 continued, Elaboration: Out-of-order processors17
1:03:39Chapter 2.3 - RV32I Registers18
1:03:39Chapter 2.3 - RV32I Registers18
1:03:39Chapter 2.3 - RV32I Registers18
1:06:10Wrap it up with the determination continue this another day
🗩
1:06:10Wrap it up with the determination continue this another day
🗩
1:06:10Wrap it up with the determination continue this another day
🗩