2.4-2.5
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0:01Recap and set the stage for the day
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0:01Recap and set the stage for the day
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0:01Recap and set the stage for the day
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1:49Review where we're at
1:49Review where we're at
1:49Review where we're at
2:27Chapter 2.4 - RV32I Integer Computation1
2:27Chapter 2.4 - RV32I Integer Computation1
2:27Chapter 2.4 - RV32I Integer Computation1
3:43A few words on the Spectre and Meltdown vulnerabilities due to branch-prediction and speculative execution
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3:43A few words on the Spectre and Meltdown vulnerabilities due to branch-prediction and speculative execution
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3:43A few words on the Spectre and Meltdown vulnerabilities due to branch-prediction and speculative execution
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8:19Chapter 2.4 continued2
8:19Chapter 2.4 continued2
8:19Chapter 2.4 continued2
10:08Point out the mistake in the book's description of the "call" pseudo-instruction3
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10:08Point out the mistake in the book's description of the "call" pseudo-instruction3
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10:08Point out the mistake in the book's description of the "call" pseudo-instruction3
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13:30Chapter 2.4 continued, on RISC-V's simple arithmetic instructions4
13:30Chapter 2.4 continued, on RISC-V's simple arithmetic instructions4
13:30Chapter 2.4 continued, on RISC-V's simple arithmetic instructions4
16:47A few words of praise for the concision of the RISC-V base ISA
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16:47A few words of praise for the concision of the RISC-V base ISA
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16:47A few words of praise for the concision of the RISC-V base ISA
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19:36Plug Casey's Meow hash,5,6 Mārtiņš's ports to ARMv87 and C without special hardware instructions,8 and Miblo's plea for a RISC-V port9 which miotatsu will happily contribute10 once RISC-V gets the proposed vector and crypto extensions11
19:36Plug Casey's Meow hash,5,6 Mārtiņš's ports to ARMv87 and C without special hardware instructions,8 and Miblo's plea for a RISC-V port9 which miotatsu will happily contribute10 once RISC-V gets the proposed vector and crypto extensions11
19:36Plug Casey's Meow hash,5,6 Mārtiņš's ports to ARMv87 and C without special hardware instructions,8 and Miblo's plea for a RISC-V port9 which miotatsu will happily contribute10 once RISC-V gets the proposed vector and crypto extensions11
37:01Chapter 2.4 continued, on RISC-V's comparison and branching instructions12
37:01Chapter 2.4 continued, on RISC-V's comparison and branching instructions12
37:01Chapter 2.4 continued, on RISC-V's comparison and branching instructions12
39:15Summarise the concept of auipc and jal to allow for 32-bit immediates
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39:15Summarise the concept of auipc and jal to allow for 32-bit immediates
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39:15Summarise the concept of auipc and jal to allow for 32-bit immediates
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46:16Figure 2.4 - The registers of RV32I13,14
46:16Figure 2.4 - The registers of RV32I13,14
46:16Figure 2.4 - The registers of RV32I13,14
52:27Chapter 2.4 continued, on the differences between RISC-V and ARM15
52:27Chapter 2.4 continued, on the differences between RISC-V and ARM15
52:27Chapter 2.4 continued, on the differences between RISC-V and ARM15
55:36Chapter 2.4 Elaboration 1 - "Bit twiddling" instructions16
55:36Chapter 2.4 Elaboration 1 - "Bit twiddling" instructions16
55:36Chapter 2.4 Elaboration 1 - "Bit twiddling" instructions16
55:54Chapter 2.4 Elaboration 2 - xor enables a magic trick17
55:54Chapter 2.4 Elaboration 2 - xor enables a magic trick17
55:54Chapter 2.4 Elaboration 2 - xor enables a magic trick17
59:47XOR swap, thanks to algebraic reversibility
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59:47XOR swap, thanks to algebraic reversibility
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59:47XOR swap, thanks to algebraic reversibility
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1:19:12Chapter 2.4 Elaboration 2 continued18
1:19:12Chapter 2.4 Elaboration 2 continued18
1:19:12Chapter 2.4 Elaboration 2 continued18
1:21:54XOR linked list, again thanks to algebraic reversibility19,20
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1:21:54XOR linked list, again thanks to algebraic reversibility19,20
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1:21:54XOR linked list, again thanks to algebraic reversibility19,20
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1:43:36Chapter 2.5 - RV32I Loads and Stores21
1:43:36Chapter 2.5 - RV32I Loads and Stores21
1:43:36Chapter 2.5 - RV32I Loads and Stores21
1:46:23Recommend Fabian's videos on CPU µArch22
1:46:23Recommend Fabian's videos on CPU µArch22
1:46:23Recommend Fabian's videos on CPU µArch22
1:50:55Chapter 2.5 continued, on differences in load / store instruction between RISC-V and MIPS and ARM23
1:50:55Chapter 2.5 continued, on differences in load / store instruction between RISC-V and MIPS and ARM23
1:50:55Chapter 2.5 continued, on differences in load / store instruction between RISC-V and MIPS and ARM23
1:51:52Recommend Robert Baruch's LMARV-1 video series24
1:51:52Recommend Robert Baruch's LMARV-1 video series24
1:51:52Recommend Robert Baruch's LMARV-1 video series24
1:53:23Chapter 2.5 Elaboration - Endianness25
1:53:23Chapter 2.5 Elaboration - Endianness25
1:53:23Chapter 2.5 Elaboration - Endianness25
1:55:27Endianness from Gulliver's Travels26
1:55:27Endianness from Gulliver's Travels26
1:55:27Endianness from Gulliver's Travels26
1:59:19That's the end of 2.5
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1:59:19That's the end of 2.5
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1:59:19That's the end of 2.5
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1:59:59krish2nasa I missed this episode
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1:59:59krish2nasa I missed this episode
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1:59:59krish2nasa I missed this episode
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2:02:06Endianness in practice in pcalc27
2:02:06Endianness in practice in pcalc27
2:02:06Endianness in practice in pcalc27
2:02:18krish2nasa I have a question for you: Is hamming distance implemented in RISC-V ISA and the compiler for more energy / code efficiency?
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2:02:18krish2nasa I have a question for you: Is hamming distance implemented in RISC-V ISA and the compiler for more energy / code efficiency?
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2:02:18krish2nasa I have a question for you: Is hamming distance implemented in RISC-V ISA and the compiler for more energy / code efficiency?
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2:05:31Endianness in practice in pcalc continued,28 including connecting to an X11 server using the ~/.Xauthority file
2:05:31Endianness in practice in pcalc continued,28 including connecting to an X11 server using the ~/.Xauthority file
2:05:31Endianness in practice in pcalc continued,28 including connecting to an X11 server using the ~/.Xauthority file
2:12:05End the episode there
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2:12:05End the episode there
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2:12:05End the episode there
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