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2.6
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Previous: '2.4-2.5'
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0:02Welcome to the stream
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0:02Welcome to the stream
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0:02Welcome to the stream
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0:54Recap the XOR tricks from last time and set the stage for the day
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0:54Recap the XOR tricks from last time and set the stage for the day
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0:54Recap the XOR tricks from last time and set the stage for the day
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3:39Chapter 2.6 - RV32I Conditional Branch1
3:39Chapter 2.6 - RV32I Conditional Branch1
3:39Chapter 2.6 - RV32I Conditional Branch1
7:50Definition: bltu (for signed array bounds-checking)2
7:50Definition: bltu (for signed array bounds-checking)2
7:50Definition: bltu (for signed array bounds-checking)2
9:46Chapter 2.6 continued, What's Different in conditional branching between RISC-V and other architectures3
9:46Chapter 2.6 continued, What's Different in conditional branching between RISC-V and other architectures3
9:46Chapter 2.6 continued, What's Different in conditional branching between RISC-V and other architectures3
10:53Chapter 2.6 Elaboration 1 - Multiword addition without condition codes4
10:53Chapter 2.6 Elaboration 1 - Multiword addition without condition codes4
10:53Chapter 2.6 Elaboration 1 - Multiword addition without condition codes4
13:37Hunt for multibyte addition example in Code: The Hidden Language of Computer Hardware and Software5
13:37Hunt for multibyte addition example in Code: The Hidden Language of Computer Hardware and Software5
13:37Hunt for multibyte addition example in Code: The Hidden Language of Computer Hardware and Software5
17:22Chapter 19 - Two Classic Microprocessors6
17:22Chapter 19 - Two Classic Microprocessors6
17:22Chapter 19 - Two Classic Microprocessors6
25:48Chapter 19 continued, on the ADC (addition with carry) and SBB (subtraction with borrow) instructions in the Intel 8080 microprocessor7
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25:48Chapter 19 continued, on the ADC (addition with carry) and SBB (subtraction with borrow) instructions in the Intel 8080 microprocessor7
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25:48Chapter 19 continued, on the ADC (addition with carry) and SBB (subtraction with borrow) instructions in the Intel 8080 microprocessor7
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36:50Imaginary RISC-V multibyte addition with carry
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36:50Imaginary RISC-V multibyte addition with carry
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36:50Imaginary RISC-V multibyte addition with carry
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39:03Chapter 19 continued, on the ADD, ADC pattern8
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39:03Chapter 19 continued, on the ADD, ADC pattern8
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39:03Chapter 19 continued, on the ADD, ADC pattern8
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39:32Chapter 19 continued, on the 8080 flags: Carry, Zero, Sign, Parity and Auxiliary Carry9
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39:32Chapter 19 continued, on the 8080 flags: Carry, Zero, Sign, Parity and Auxiliary Carry9
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39:32Chapter 19 continued, on the 8080 flags: Carry, Zero, Sign, Parity and Auxiliary Carry9
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41:41Thoughts on the differing complexity and terseness of architectures with (8080) and without (RISC-V) status flags
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41:41Thoughts on the differing complexity and terseness of architectures with (8080) and without (RISC-V) status flags
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41:41Thoughts on the differing complexity and terseness of architectures with (8080) and without (RISC-V) status flags
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45:26Chapter 2.6 Elaboration 1 - Multiword addition without condition codes10
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45:26Chapter 2.6 Elaboration 1 - Multiword addition without condition codes10
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45:26Chapter 2.6 Elaboration 1 - Multiword addition without condition codes10
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55:12Wrap this up
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55:12Wrap this up
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55:12Wrap this up
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