Register
2.6
?
?

Keyboard Navigation

Global Keys

[, < / ], > Jump to previous / next episode
W, K, P / S, J, N Jump to previous / next marker
t / T Toggle theatre / SUPERtheatre mode
V Revert filter to original state Y Select link (requires manual Ctrl-c)

Menu toggling

q Quotes r References f Filter y Link c Credits

In-Menu Movement

a
w
s
d
h j k l


Quotes and References Menus

Enter Jump to timecode

Quotes, References and Credits Menus

o Open URL (in new tab)

Filter Menu

x, Space Toggle category and focus next
X, ShiftSpace Toggle category and focus previous
v Invert topics / media as per focus

Filter and Link Menus

z Toggle filter / linking mode

Credits Menu

Enter Open URL (in new tab)
0:02Welcome to the stream
🗩
0:02Welcome to the stream
🗩
0:02Welcome to the stream
🗩
0:54Recap the XOR tricks from last time and set the stage for the day
🗩
0:54Recap the XOR tricks from last time and set the stage for the day
🗩
0:54Recap the XOR tricks from last time and set the stage for the day
🗩
3:39Chapter 2.6 - RV32I Conditional Branch1
3:39Chapter 2.6 - RV32I Conditional Branch1
3:39Chapter 2.6 - RV32I Conditional Branch1
7:50Definition: bltu (for signed array bounds-checking)2
7:50Definition: bltu (for signed array bounds-checking)2
7:50Definition: bltu (for signed array bounds-checking)2
9:46Chapter 2.6 continued, What's Different in conditional branching between RISC-V and other architectures3
9:46Chapter 2.6 continued, What's Different in conditional branching between RISC-V and other architectures3
9:46Chapter 2.6 continued, What's Different in conditional branching between RISC-V and other architectures3
10:53Chapter 2.6 Elaboration 1 - Multiword addition without condition codes4
10:53Chapter 2.6 Elaboration 1 - Multiword addition without condition codes4
10:53Chapter 2.6 Elaboration 1 - Multiword addition without condition codes4
13:37Hunt for multibyte addition example in Code: The Hidden Language of Computer Hardware and Software5
13:37Hunt for multibyte addition example in Code: The Hidden Language of Computer Hardware and Software5
13:37Hunt for multibyte addition example in Code: The Hidden Language of Computer Hardware and Software5
17:22Chapter 19 - Two Classic Microprocessors6
17:22Chapter 19 - Two Classic Microprocessors6
17:22Chapter 19 - Two Classic Microprocessors6
25:48Chapter 19 continued, on the ADC (addition with carry) and SBB (subtraction with borrow) instructions in the Intel 8080 microprocessor7
📖
🖌
25:48Chapter 19 continued, on the ADC (addition with carry) and SBB (subtraction with borrow) instructions in the Intel 8080 microprocessor7
📖
🖌
25:48Chapter 19 continued, on the ADC (addition with carry) and SBB (subtraction with borrow) instructions in the Intel 8080 microprocessor7
📖
🖌
36:50Imaginary RISC-V multibyte addition with carry
🖌
36:50Imaginary RISC-V multibyte addition with carry
🖌
36:50Imaginary RISC-V multibyte addition with carry
🖌
39:03Chapter 19 continued, on the ADD, ADC pattern8
📖
39:03Chapter 19 continued, on the ADD, ADC pattern8
📖
39:03Chapter 19 continued, on the ADD, ADC pattern8
📖
39:32Chapter 19 continued, on the 8080 flags: Carry, Zero, Sign, Parity and Auxiliary Carry9
📖
39:32Chapter 19 continued, on the 8080 flags: Carry, Zero, Sign, Parity and Auxiliary Carry9
📖
39:32Chapter 19 continued, on the 8080 flags: Carry, Zero, Sign, Parity and Auxiliary Carry9
📖
41:41Thoughts on the differing complexity and terseness of architectures with (8080) and without (RISC-V) status flags
🖌
41:41Thoughts on the differing complexity and terseness of architectures with (8080) and without (RISC-V) status flags
🖌
41:41Thoughts on the differing complexity and terseness of architectures with (8080) and without (RISC-V) status flags
🖌
45:26Chapter 2.6 Elaboration 1 - Multiword addition without condition codes10
📖
🖌
45:26Chapter 2.6 Elaboration 1 - Multiword addition without condition codes10
📖
🖌
45:26Chapter 2.6 Elaboration 1 - Multiword addition without condition codes10
📖
🖌
55:12Wrap this up
🗩
55:12Wrap this up
🗩
55:12Wrap this up
🗩
56:05krish2nasa Thanks
🗪
56:05krish2nasa Thanks
🗪
56:05krish2nasa Thanks
🗪
You have arrived at the (current) end of Risc-V Book Club