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RISCY BUSINESS»Episode Guide
Getting Back to the Code
References ▼
Wikipedia
Sign extension
[1]0:57
Wikipedia
Two's complement
[2]10:07
RISC-V"
User-Level ISA Specification v2.1
[3]15:19
GitHub
instructions.scala
[4]41:25
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0:08Recap and set the stage for the day
0:08Recap and set the stage for the day
0:08Recap and set the stage for the day
0:57Sign extension in two's complement1
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0:57Sign extension in two's complement1
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0:57Sign extension in two's complement1
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7:45hossein1387 You can do a two's complement on 1000_0000 to get the positive value
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7:45hossein1387 You can do a two's complement on 1000_0000 to get the positive value
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7:45hossein1387 You can do a two's complement on 1000_0000 to get the positive value
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10:07Research setting only the most significant bit in two's complement2
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10:07Research setting only the most significant bit in two's complement2
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10:07Research setting only the most significant bit in two's complement2
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15:19Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension3
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15:19Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension3
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15:19Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension3
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19:25Read about the Integer Register-Immediate Instructions
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19:25Read about the Integer Register-Immediate Instructions
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19:25Read about the Integer Register-Immediate Instructions
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22:54Adding unsigned immediates
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22:54Adding unsigned immediates
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22:54Adding unsigned immediates
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23:25hossein1387 For the adder it does not matter if it's a sign or signed
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23:25hossein1387 For the adder it does not matter if it's a sign or signed
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23:25hossein1387 For the adder it does not matter if it's a sign or signed
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26:48Adding unsigned 42 to 128 using sign extension (with incorrect results)
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26:48Adding unsigned 42 to 128 using sign extension (with incorrect results)
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26:48Adding unsigned 42 to 128 using sign extension (with incorrect results)
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31:47hossein1387 But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder
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31:47hossein1387 But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder
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31:47hossein1387 But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder
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34:27hossein1387 I have a list of instructions for RISC-V and I can only see ADD and ADDI
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34:27hossein1387 I have a list of instructions for RISC-V and I can only see ADD and ADDI
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34:27hossein1387 I have a list of instructions for RISC-V and I can only see ADD and ADDI
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35:28Consider unsigned immediate adding to be a gotcha if coding in assembly
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35:28Consider unsigned immediate adding to be a gotcha if coding in assembly
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35:28Consider unsigned immediate adding to be a gotcha if coding in assembly
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38:08hossein1387 Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW
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38:08hossein1387 Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW
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38:08hossein1387 Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW
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40:27hossein1387 By the way I am reading the RTL for instructions
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40:27hossein1387 By the way I am reading the RTL for instructions
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40:27hossein1387 By the way I am reading the RTL for instructions
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41:25hossein1387 4
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41:25hossein1387 4
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41:25hossein1387 4
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44:53Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()
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44:53Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()
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44:53Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()
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50:29Read about the rs1 and rd, and RISC-V user-level base integer register state
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50:29Read about the rs1 and rd, and RISC-V user-level base integer register state
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50:29Read about the rs1 and rd, and RISC-V user-level base integer register state
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54:48Read about the types of immediate produced by RISC-V instructions
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54:48Read about the types of immediate produced by RISC-V instructions
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54:48Read about the types of immediate produced by RISC-V instructions
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1:01:09Determine to ask in the SiFive Forums about the < 32 test in clear_csr()
1:01:09Determine to ask in the SiFive Forums about the < 32 test in clear_csr()
1:01:09Determine to ask in the SiFive Forums about the < 32 test in clear_csr()