Jump to Content
Register
Forgot your password?
Third-party login
Log in with Discord

RISCY BUSINESS
Blog
Forums
Episode Guide
twitter
RISCY BUSINESS»Episode Guide
Getting Back to the Code
References ▼
Wikipedia
Sign extension
[1]0:57
Wikipedia
Two's complement
[2]10:07
RISC-V"
User-Level ISA Specification v2.1
[3]15:19
GitHub
instructions.scala
[4]41:25
Filter mode:
Topics
asm
(null topic)
Media
🗪Chat Comment
🖮Programming🟉
📖Research
🖌Whiteboard
🎭
🏟
🔗
Link to: current timestamp
Credits
Host
Neo Ar
Indexer
Matt Mascarenhas
?
?

Keyboard Navigation

Global Keys

[, < / ], > Jump to previous / next episode
W, K, P / S, J, N Jump to previous / next marker
t / T Toggle theatre / SUPERtheatre mode
V Revert filter to original state Y Select link (requires manual Ctrl-c)

Menu toggling

q Quotes r References f Filter y Link c Credits

In-Menu Movement

a
w
s
d
h j k l
←
↑
↓
→

Quotes and References Menus

Enter Jump to timecode

Quotes, References and Credits Menus

o Open URL (in new tab)

Filter Menu

x, Space Toggle category and focus next
X, ShiftSpace Toggle category and focus previous
v Invert topics / media as per focus

Filter and Link Menus

z Toggle filter / linking mode

Credits Menu

Enter Open URL (in new tab)
0:08Recap and set the stage for the day
0:08Recap and set the stage for the day
0:08Recap and set the stage for the day
0:57Sign extension in two's complement1
📖
🖌
0:57Sign extension in two's complement1
📖
🖌
0:57Sign extension in two's complement1
📖
🖌
7:45hossein1387 You can do a two's complement on 1000_0000 to get the positive value
🗪
7:45hossein1387 You can do a two's complement on 1000_0000 to get the positive value
🗪
7:45hossein1387 You can do a two's complement on 1000_0000 to get the positive value
🗪
10:07Research setting only the most significant bit in two's complement2
📖
10:07Research setting only the most significant bit in two's complement2
📖
10:07Research setting only the most significant bit in two's complement2
📖
15:19Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension3
📖
15:19Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension3
📖
15:19Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension3
📖
19:25Read about the Integer Register-Immediate Instructions
📖
19:25Read about the Integer Register-Immediate Instructions
📖
19:25Read about the Integer Register-Immediate Instructions
📖
22:54Adding unsigned immediates
🖌
22:54Adding unsigned immediates
🖌
22:54Adding unsigned immediates
🖌
23:25hossein1387 For the adder it does not matter if it's a sign or signed
🗪
23:25hossein1387 For the adder it does not matter if it's a sign or signed
🗪
23:25hossein1387 For the adder it does not matter if it's a sign or signed
🗪
26:48Adding unsigned 42 to 128 using sign extension (with incorrect results)
🖌
26:48Adding unsigned 42 to 128 using sign extension (with incorrect results)
🖌
26:48Adding unsigned 42 to 128 using sign extension (with incorrect results)
🖌
31:47hossein1387 But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder
🗪
31:47hossein1387 But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder
🗪
31:47hossein1387 But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder
🗪
34:27hossein1387 I have a list of instructions for RISC-V and I can only see ADD and ADDI
🗪
34:27hossein1387 I have a list of instructions for RISC-V and I can only see ADD and ADDI
🗪
34:27hossein1387 I have a list of instructions for RISC-V and I can only see ADD and ADDI
🗪
35:28Consider unsigned immediate adding to be a gotcha if coding in assembly
📖
🖌
35:28Consider unsigned immediate adding to be a gotcha if coding in assembly
📖
🖌
35:28Consider unsigned immediate adding to be a gotcha if coding in assembly
📖
🖌
38:08hossein1387 Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW
🗪
38:08hossein1387 Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW
🗪
38:08hossein1387 Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW
🗪
40:27hossein1387 By the way I am reading the RTL for instructions
🗪
40:27hossein1387 By the way I am reading the RTL for instructions
🗪
40:27hossein1387 By the way I am reading the RTL for instructions
🗪
41:25hossein1387 4
🗪
41:25hossein1387 4
🗪
41:25hossein1387 4
🗪
44:53Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()
📖
44:53Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()
📖
44:53Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()
📖
50:29Read about the rs1 and rd, and RISC-V user-level base integer register state
📖
50:29Read about the rs1 and rd, and RISC-V user-level base integer register state
📖
50:29Read about the rs1 and rd, and RISC-V user-level base integer register state
📖
54:48Read about the types of immediate produced by RISC-V instructions
📖
54:48Read about the types of immediate produced by RISC-V instructions
📖
54:48Read about the types of immediate produced by RISC-V instructions
📖
1:01:09Determine to ask in the SiFive Forums about the < 32 test in clear_csr()
1:01:09Determine to ask in the SiFive Forums about the < 32 test in clear_csr()
1:01:09Determine to ask in the SiFive Forums about the < 32 test in clear_csr()