Register
BlogForumsWikiLibraryEpisode Guide
Studying the Machine Interrupt Registers
References ▼
GitHub
instructions.scala
[1]9:03
Wikipedia
Register-transfer level
[2]9:03
SiFive Forums
Confusion Regarding Freedom E SDK inline asm
[3]15:55
RISC-V
User-Level ISA Specification v2.1
[4]22:24
ericw.
A Tiny Guide to GCC Inline Assembly
[5]28:53
RISC-V
Draft Privileged ISA Specification v1.9.1
[6]40:21
Filter mode:
Topics
asm
hardware
(null topic)
Media
🖮Programming🟉
📖Research
🖌Whiteboard
🎭
🏟
🔗
Link to: current timestamp
Credits
Host
Mio Iwakura
Indexer
Matt Mascarenhas
?
?

Keyboard Navigation

Global Keys

[, < / ], > Jump to previous / next episode
W, K, P / S, J, N Jump to previous / next marker
t / T Toggle theatre / SUPERtheatre mode
V Revert filter to original state Y Select link (requires manual Ctrl-c)

Menu toggling

q Quotes r References f Filter y Link c Credits

In-Menu Movement

a
w
s
d
h j k l
←
↑
↓
→

Quotes and References Menus

Enter Jump to timecode

Quotes, References and Credits Menus

o Open URL (in new tab)

Filter Menu

x, Space Toggle category and focus next
X, ShiftSpace Toggle category and focus previous
v Invert topics / media as per focus

Filter and Link Menus

z Toggle filter / linking mode

Credits Menu

Enter Open URL (in new tab)
0:06Recap and set the stage for the day
0:06Recap and set the stage for the day
0:06Recap and set the stage for the day
0:51Intuition on two's complement
🖌
0:51Intuition on two's complement
🖌
0:51Intuition on two's complement
🖌
4:10We are counting with zeroes
🖌
4:10We are counting with zeroes
🖌
4:10We are counting with zeroes
🖌
9:03Revisit instructions.scala1 and research register-transfer level2
📖
9:03Revisit instructions.scala1 and research register-transfer level2
📖
9:03Revisit instructions.scala1 and research register-transfer level2
📖
15:55Come to understand how to specify that rs1 represents an immediate or a register, thanks to the reply to the "Confusion Regarding Freedom E SDK inline asm" forum thread3
🖌
15:55Come to understand how to specify that rs1 represents an immediate or a register, thanks to the reply to the "Confusion Regarding Freedom E SDK inline asm" forum thread3
🖌
15:55Come to understand how to specify that rs1 represents an immediate or a register, thanks to the reply to the "Confusion Regarding Freedom E SDK inline asm" forum thread3
🖌
18:25Read clear_csr() to put csrrc into perspective with our new understanding of pseudo-instructions and the i vs r hints
📖
🖌
18:25Read clear_csr() to put csrrc into perspective with our new understanding of pseudo-instructions and the i vs r hints
📖
🖌
18:25Read clear_csr() to put csrrc into perspective with our new understanding of pseudo-instructions and the i vs r hints
📖
🖌
22:24Read about CSRRCI in the CSR Instructions section of the User-Level ISA Specification4
📖
22:24Read about CSRRCI in the CSR Instructions section of the User-Level ISA Specification4
📖
22:24Read about CSRRCI in the CSR Instructions section of the User-Level ISA Specification4
📖
23:05Walk through clear_csr() again
📖
23:05Walk through clear_csr() again
📖
23:05Walk through clear_csr() again
📖
28:53GNU Assembly Syntax: Constraints and Syntax5
📖
🖌
28:53GNU Assembly Syntax: Constraints and Syntax5
📖
🖌
28:53GNU Assembly Syntax: Constraints and Syntax5
📖
🖌
35:15Continue reading clear_csr()
📖
35:15Continue reading clear_csr()
📖
35:15Continue reading clear_csr()
📖
40:21Pop back up to the top of the stack, to reset_demo(), and read about the currently allocated RISC-V machine-level CSR addresses6
📖
40:21Pop back up to the top of the stack, to reset_demo(), and read about the currently allocated RISC-V machine-level CSR addresses6
📖
40:21Pop back up to the top of the stack, to reset_demo(), and read about the currently allocated RISC-V machine-level CSR addresses6
📖
44:11Read about Machine Interrupt Registers, including the mie (machine interrupt-enable) register
📖
44:11Read about Machine Interrupt Registers, including the mie (machine interrupt-enable) register
📖
44:11Read about Machine Interrupt Registers, including the mie (machine interrupt-enable) register
📖
49:26Note how common it is in plic_driver.c for us to compute an address of a memory mapped register in order to mess with interrupts
📖
49:26Note how common it is in plic_driver.c for us to compute an address of a memory mapped register in order to mess with interrupts
📖
49:26Note how common it is in plic_driver.c for us to compute an address of a memory mapped register in order to mess with interrupts
📖
51:45A few words on the sponge mode that we're in
51:45A few words on the sponge mode that we're in
51:45A few words on the sponge mode that we're in
52:50Continue reading about the Machine Interrupt Registers
📖
52:50Continue reading about the Machine Interrupt Registers
📖
52:50Continue reading about the Machine Interrupt Registers
📖
58:33Return to demo_gpio.c and come to understand the clear_csr() calls in relation to the documentation
📖
58:33Return to demo_gpio.c and come to understand the clear_csr() calls in relation to the documentation
📖
58:33Return to demo_gpio.c and come to understand the clear_csr() calls in relation to the documentation
📖
1:06:48We're out of time for today
1:06:48We're out of time for today
1:06:48We're out of time for today

Want to support this annotated episode guide?

Miblo is presently its sole maintainer, annotating live.